1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
A NAND type flash memory having a floating gate is now confronted with a problem that the structure of memory cell (cell transistor) has to be changed because of the generation of interference between the neighboring cells and the difficulty in embedding an insulating film between the neighboring cells, owing to the persistent trend to further increase the fineness of a cell pattern.
A memory cell having a charge trapping layer consisting of an insulating film is considered as the most prospective as a structure of a memory cell of the next generation wherein the gate length is in the order of 20 nm. The memory cell of this sort is generally called a Metal/Oxide film/Nitride film/Oxide film/Semiconductor (MONOS). This MONOS memory cell is configured to have a gate stack structure, which is formed on a channel between source/drain diffusion regions formed in a surface region of a Si substrate, and is constituted by a tunnel insulating film for passing a writing/erasing charge, a silicon nitride film functioning as a charge trapping layer, a silicon oxide film functioning as an insulating film which is capable of obstructing electric current, and a gate electrode formed on the silicon oxide film and made of a metal. This MONOS memory cell is constructed as a planar cell, thereby overcoming the aforementioned problem with which the conventional floating gate type NAND flash memory has been troubled.
In this MONOS memory cell or in the conventional floating gate type memory cell, the employment of an alumina-based high-dielectric constant film is now studied in order to inhibit a high field leak current by increasing the film thickness of the block insulating film and by decreasing the effective electric field by enabling a portion of the block insulating film to trap electrons or in order to inhibit the inter-cell interference by decreasing EOT through the thinning of the film thickness of the charge trapping layer by increasing the trapping density of the charge trapping layer.
The MONOS memory cell, however, is still accompanied with many problems to be solved in terms of performance, such as the magnitude of variation of threshold voltage (hereinafter referred to simply as Vth), write/erase endurance and data retention characteristics. In addition to these problems, the MONOS memory cell is also accompanied with a problem that the threshold voltage thereof employed on the occasions of writing and erasing does not adapted to threshold voltage which is required when the MONOS memory cell is utilized as a NAND type flash memory which is suited for use as a memory of high density.
As a matter of fact, in the case of the NAND type flash memory, the threshold voltage after the writing operation is required to be Vth>0 and the threshold voltage after the erasing operation is required to be Vth<0. Whereas, in the case of the NOR type flash memory, the threshold voltage after the writing as well as after the erasing is generally required to be Vth>0. Even in the case of the MONOS memory device having most excellent in performance now, it cannot secure a sufficiently large negative Vth as a threshold voltage after the erasing, even though the Vth after the writing can be sufficiently increased. Thus, it cannot realize so-called over-erasing of charge.
Accordingly, even though the MONOS memory device can be easily applied to the NOR type flash memory, there is still a problem of the adjustment of threshold voltage if the MONOS memory device is to be applied to the NAND type flash memory.
Although it is of course conceivable, for the adjustment of the threshold voltage, to adopt a method wherein the dopant impurity concentration in the channel region of a Si substrate is adjusted, it will lead to a prominent increase in short channel effects as the fineness of memory cell is further advanced, thereby necessitating the raising of the neutral threshold voltage (the initial threshold voltage before writing/erasing) in order to suppress the short channel effects. On the other hand, as described above, since there is an increasing trend to lower the neutral threshold voltage in the operation of the NAND type flash memory, the aforementioned method goes against this trend to lower the neutral threshold voltage as there are persistent requirements to further enhance the fineness of the memory cell, thus indicating that the aforementioned problem cannot be solved simply through the adjustment of dopant impurity concentration in the channel region.
In addition to these problems, the MONOS memory cell is also required to exhibit so-called field relaxation effects. Namely, a plurality of block layers are laminated so as to provide a layer for accumulating a negative (fixed) charge in the block layers, thereby relaxing the electric field at the interfaces of the opposite ends of the block insulating films on the occasion of a writing/erasing operation (especially, on the occasion of an erasing operation) of the memory cell. As a result of the field relaxation effects, the generation of leakage current from a controlling electrode can be minimized, thus realizing high-speed erasing. One example of doping boron in a case where a silicon nitride film is employed is described in JP-A 2004-363329. This patent document discloses in detail about the theoretical background for realizing high-speed erasing through the relaxation of electric field.
Other than the aforementioned requirements, it is of course required to create a design prescription for the material itself for building up electron trap levels which are suited for the trap (writing) or detrapping (erasing) or retention of charge which is most important as a charge trapping layer.
As described above, in the case where an alumina-based insulating film is employed, there is a problem that there is no clear design prescription for the material for building up deep electron trap levels (for relaxing electric field) which are suited for the block insulating film, for building up defect levels having the depth which is suited for both writing/erasing required for the charge trapping layer (for efficient writing/erasing/retention characteristics), or for building up electron occupied levels which are capable of adjusting the threshold by way of over-erasing which is applicable to the NAND type flash memory (over-erasing directivity).